Modified SIMD architecture suitable for single-chip implementation

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dc.creatorMakino, Junichiro
dc.date2005-09-11
dc.date.accessioned2026-07-07T02:18:37Z
dc.date.available2026-07-07T02:18:37Z
dc.descriptionWe describe a modified SIMD architecture suitable for single-chip integration of a large number of processing elements, such as 1,000 or more. Important differences from traditional SIMD designs are: a) The size of the memory per processing elements is kept small. b) The processors are organized into groups, each with a small buffer memory. Reduction operation over the groups is done in hardware. The first change allows us to integrate a very large number of processing elements into a single chip. The second change allows us to achieve a close-to-peak performance for many scientific applications like particle-based simulations and dense-matrix operations.
dc.identifierhttps://arxiv.org/abs/astro-ph/0509278
dc.identifierhttp://arxiv.org/abs/astro-ph/0509278
dc.identifier.urihttp://salesiana.dossiersoluciones.com/handle/123456789/9555
dc.subjectAstrophysics
dc.titleModified SIMD architecture suitable for single-chip implementation
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