Optimal Memoryless Encoding for Low Power Off-Chip Data Buses

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dc.creatorChee, Yeow Meng
dc.creatorColbourn, Charles J.
dc.creatorLing, Alan C. H.
dc.date2007-12-17
dc.date.accessioned2026-07-07T08:49:37Z
dc.date.available2026-07-07T08:49:37Z
dc.descriptionOff-chip buses account for a significant portion of the total system power consumed in embedded systems. Bus encoding schemes have been proposed to minimize power dissipation, but none has been demonstrated to be optimal with respect to any measure. In this paper, we give the first provably optimal and explicit (polynomial-time constructible) families of memoryless codes for minimizing bit transitions in off-chip buses. Our results imply that having access to a clock does not make a memoryless encoding scheme that minimizes bit transitions more powerful.
dc.descriptionProceedings of the 2006 IEEE/ACM international Conference on Computer-Aided Design (San Jose, California, November 05 - 09, 2006). ICCAD '06. ACM, New York, NY, 369-374
dc.identifierhttps://arxiv.org/abs/0712.2640
dc.identifierhttp://arxiv.org/abs/0712.2640
dc.identifierdoi:10.1145/1233501.1233575
dc.identifier.urihttp://salesiana.dossiersoluciones.com/handle/123456789/144365
dc.subjectHardware Architecture
dc.subjectDiscrete Mathematics
dc.subjectInformation Theory
dc.subjectB.4.3; B.m; E.4
dc.titleOptimal Memoryless Encoding for Low Power Off-Chip Data Buses
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