Cell Architecture for Nanoelectronic Design
| dc.creator | Martorell, F. | |
| dc.creator | Rubio, A. | |
| dc.date | 2007-08-10 | |
| dc.date.accessioned | 2026-07-07T08:23:08Z | |
| dc.date.available | 2026-07-07T08:23:08Z | |
| dc.description | Several nanoelectronic devices have been already proved. However, no architecture which makes use of them provides a feasible opportunity to build medium/large systems. Nanoarchitecture proposals only solve a small part of the problems needed to achieve a real design. In this paper, we propose and analyze a cell architecture that overcomes most of those at the gate level. Using the cell structure we build 2 and 3-input NAND gates showing their error probabilities. Finally, we outline a method to further improve the structure's tolerance by taking advantage of interferences among nanodevices. Using this improvement we show that it is possible to reduce the output standard deviation by a factor larger than $\sqrt{2}$ and restitute the signal levels using nanodevices. | |
| dc.description | Submitted on behalf of TIMA Editions (http://irevues.inist.fr/tima-editions) | |
| dc.identifier | https://arxiv.org/abs/0708.1454 | |
| dc.identifier | http://arxiv.org/abs/0708.1454 | |
| dc.identifier | Dans European Nano Systems Worshop - ENS 2006, Paris : France (2006) | |
| dc.identifier.uri | http://salesiana.dossiersoluciones.com/handle/123456789/135885 | |
| dc.subject | Materials Science | |
| dc.title | Cell Architecture for Nanoelectronic Design | |
| dc.type | text |