Hierarchical Triple-Modular Redundancy (H-TMR) Network For Digital Systems
| dc.creator | Alagoz, B. Baykant | |
| dc.date | 2009-02-02 | |
| dc.date | 2009-02-03 | |
| dc.date.accessioned | 2026-07-07T12:36:57Z | |
| dc.date.available | 2026-07-07T12:36:57Z | |
| dc.description | Hierarchical application of Triple-Modular Redundancy (TMR) increases fault tolerance of digital Integrated Circuit (IC). In this paper, a simple probabilistic model was proposed for analysis of fault masking performance of hierarchical TMR networks. Performance improvements obtained by second order TMR network were theoretically compared with first order TMR network. | |
| dc.description | Proposition section was added | |
| dc.identifier | https://arxiv.org/abs/0902.0241 | |
| dc.identifier | http://arxiv.org/abs/0902.0241 | |
| dc.identifier | OncuBilim Algorithm And Systems Labs. Vol.08, Art.No:05,(2008) | |
| dc.identifier.uri | http://salesiana.dossiersoluciones.com/handle/123456789/218271 | |
| dc.subject | Other Computer Science | |
| dc.title | Hierarchical Triple-Modular Redundancy (H-TMR) Network For Digital Systems | |
| dc.type | text |