Tree Parity Machine Rekeying Architectures
| dc.creator | Volkmer, Markus | |
| dc.creator | Wallner, Sebastian | |
| dc.date | 2005-02-14 | |
| dc.date.accessioned | 2026-07-07T03:22:32Z | |
| dc.date.available | 2026-07-07T03:22:32Z | |
| dc.description | The necessity to secure the communication between hardware components in embedded systems becomes increasingly important with regard to the secrecy of data and particularly its commercial use. We suggest a low-cost (i.e. small logic-area) solution for flexible security levels and short key lifetimes. The basis is an approach for symmetric key exchange using the synchronisation of Tree Parity Machines. Fast successive key generation enables a key exchange within a few milliseconds, given realistic communication channels with a limited bandwidth. For demonstration we evaluate characteristics of a standard-cell ASIC design realisation as IP-core in 0.18-micrometer CMOS-technology. | |
| dc.identifier | https://arxiv.org/abs/cs/0502062 | |
| dc.identifier | http://arxiv.org/abs/cs/0502062 | |
| dc.identifier | IEEE Transactions on Computers Vol. 54 No. 4, pp. 421-427, April 2005 | |
| dc.identifier.uri | http://salesiana.dossiersoluciones.com/handle/123456789/32632 | |
| dc.subject | Cryptography and Security | |
| dc.subject | Hardware Architecture | |
| dc.subject | K.4.4.f; K.6.5.a; B.7.1.b; C.3.h; J.9.d | |
| dc.title | Tree Parity Machine Rekeying Architectures | |
| dc.type | text |