Statistical Yield Modeling for IC Manufacture: Hierarchical Fault Distributions

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dc.creatorBogdanov, Yu. I.
dc.creatorBogdanova, N. A.
dc.creatorDshkhunyan, V. L.
dc.date2003-03-10
dc.date.accessioned2026-07-07T05:48:54Z
dc.date.available2026-07-07T05:48:54Z
dc.descriptionA hierarchical approach to the construction of compound distributions for process-induced faults in IC manufacture is proposed. Within this framework, the negative binomial distribution and the compound binomial distribution are treated as level-1 models. The hierarchical approach to fault distribution offers an integrated picture of how fault density varies from region to region within a wafer, from wafer to wafer within a batch, and so on. A theory of compound-distribution hierarchies is developed by means of generating functions. With respect to applications, hierarchies of yield means and yield probability-density functions are considered and an in-process measure of yield loss is introduced. It is shown that the hierarchical approach naturally embraces the Bayesian approach.
dc.descriptionOAO Angstrem, Moscow Institute of Electronic Engineering (Technical University), Moscow, Russia, 19 pages, 2 figures
dc.identifierhttps://arxiv.org/abs/physics/0303039
dc.identifierhttp://arxiv.org/abs/physics/0303039
dc.identifierRussian Microelectronics, 2003, V.32, N 1, P. 51
dc.identifier.urihttp://salesiana.dossiersoluciones.com/handle/123456789/85201
dc.subjectData Analysis, Statistics and Probability
dc.subjectStatistical Mechanics
dc.titleStatistical Yield Modeling for IC Manufacture: Hierarchical Fault Distributions
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