Architecture-Dependent Execution Time of Shor's Algorithm
| dc.creator | Van Meter, Rodney | |
| dc.creator | Itoh, Kohei M. | |
| dc.creator | Ladd, Thaddeus D. | |
| dc.date | 2005-07-04 | |
| dc.date | 2006-05-25 | |
| dc.date.accessioned | 2026-07-07T06:43:35Z | |
| dc.date.available | 2026-07-07T06:43:35Z | |
| dc.description | We show how the execution time of algorithms on quantum computers depends on the architecture of the quantum computer, the choice of algorithms (including subroutines such as arithmetic), and the ``clock speed'' of the quantum computer. The primary architectural features of interest are the ability to execute multiple gates concurrently, the number of application-level qubits available, and the interconnection network of qubits. We analyze Shor's algorithm for factoring large numbers in this context. Our results show that, if arbitrary interconnection of qubits is possible, a machine with an application-level clock speed of as low as one-third of a (possibly encoded) gate per second could factor a 576-bit number in under one month, potentially outperforming a large network of classical computers. For nearest-neighbor-only architectures, a clock speed of around twenty-seven gates per second is required. | |
| dc.description | 6 pages, 2 figures, single-column World Scientific format. v2: published version, shortened text, slightly revised performance numbers | |
| dc.identifier | https://arxiv.org/abs/quant-ph/0507023 | |
| dc.identifier | http://arxiv.org/abs/quant-ph/0507023 | |
| dc.identifier | Proc. Mesoscopic Superconductivity + Spintronics 2006 | |
| dc.identifier.uri | http://salesiana.dossiersoluciones.com/handle/123456789/102468 | |
| dc.subject | Quantum Physics | |
| dc.title | Architecture-Dependent Execution Time of Shor's Algorithm | |
| dc.type | text |