Noise Limited Computational Speed

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dc.creatorGammaitoni, Luca
dc.date2007-02-11
dc.date.accessioned2026-07-07T08:48:01Z
dc.date.available2026-07-07T08:48:01Z
dc.descriptionIn modern transistor based logic gates, the impact of noise on computation has become increasingly relevant since the voltage scaling strategy, aimed at decreasing the dissipated power, has increased the probability of error due to the reduced switching threshold voltages. In this paper we discuss the role of noise in a two state model that mimic the dynamics of standard logic gates and show that the presence of the noise sets a fundamental limit to the computing speed. An optimal idle time interval that minimizes the error probability, is derived.
dc.identifierhttps://arxiv.org/abs/cs/0702062
dc.identifierhttp://arxiv.org/abs/cs/0702062
dc.identifierL. Gammaitoni, Applied Physics Letters, 11/2007, Volume 91, p.3, (2007)
dc.identifierdoi:10.1063/1.2817968
dc.identifier.urihttp://salesiana.dossiersoluciones.com/handle/123456789/143800
dc.subjectHardware Architecture
dc.subjectPerformance
dc.subjectB.1.3; B.7.0; B.8.1; B.8.2
dc.titleNoise Limited Computational Speed
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