Fabrication of 3D Packaging TSV using DRIE

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dc.creatorPuech, M.
dc.creatorThevenoud, Jean-Marc
dc.creatorGruffat, J. M.
dc.creatorLaunay, N.
dc.creatorArnal, N.
dc.creatorGodinat, P.
dc.date2008-05-07
dc.date.accessioned2026-07-07T12:18:45Z
dc.date.available2026-07-07T12:18:45Z
dc.descriptionEmerging 3D chips stacking and MEMS/Sensors packaging technologies are using DRIE (Deep Reactive Ion Etching) to etch through-silicon via (TSV) for advanced interconnections. The interconnection step can be done prior to or post CMOS manufacturing, each requiring different etch process performances. A review of the DRIE capability in terms of etching profile, etch rate, etch depth has been carried out. Excellent tool flexibility allows a wide range of basic and complex profiles to be achieved. Unlike other techniques, DRIE has the capability to etch feature sizes ranging from sub-micron to millimeter width. The main specificity of the DRIE is that etch rate is sensitive to the total exposed area and the aspect ratio. For the TSV applications, where the total exposed area is lower than 10%, high etch rates are achievable. A study has also been done to highlight the importance of via profile for the success of the refilling step. In addition, due to the high flexibility of DRIE, we also explore the capability of using this technique for wafer thinning and plasma die separation.
dc.descriptionSubmitted on behalf of EDA Publishing Association (http://irevues.inist.fr/handle/2042/16838)
dc.identifierhttps://arxiv.org/abs/0805.0919
dc.identifierhttp://arxiv.org/abs/0805.0919
dc.identifierDans Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS - DTIP 2008, Nice : France (2008)
dc.identifier.urihttp://salesiana.dossiersoluciones.com/handle/123456789/212517
dc.subjectOther Computer Science
dc.titleFabrication of 3D Packaging TSV using DRIE
dc.typetext

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