A 8 bits Pipeline Analog to Digital Converter Design for High Speed Camera Application

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dc.creatorPrasetyo, Eri
dc.creatorAfandi, Hamzah
dc.creatorGinhac, Nurul Huda Dominique
dc.creatorPaindavoine, Michel
dc.date2008-08-04
dc.date.accessioned2026-07-07T09:54:31Z
dc.date.available2026-07-07T09:54:31Z
dc.description- This paper describes a pipeline analog-to-digital converter is implemented for high speed camera. In the pipeline ADC design, prime factor is designing operational amplifier with high gain so ADC have been high speed. The other advantage of pipeline is simple on concept, easy to implement in layout and have flexibility to increase speed. We made design and simulation using Mentor Graphics Software with 0.6 μm CMOS technology with a total power dissipation of 75.47 mW. Circuit techniques used include a precise comparator, operational amplifier and clock management. A switched capacitor is used to sample and multiplying at each stage. Simulation a worst case DNL and INL of 0.75 LSB. The design operates at 5 V dc. The ADC achieves a SNDR of 44.86 dB. keywords: pipeline, switched capacitor, clock management
dc.description5 pages, 5 authors, conference
dc.identifierhttps://arxiv.org/abs/0808.0374
dc.identifierhttp://arxiv.org/abs/0808.0374
dc.identifierEEPIS, 2007
dc.identifier.urihttp://salesiana.dossiersoluciones.com/handle/123456789/166343
dc.subjectRobotics
dc.subjectComputer Vision and Pattern Recognition
dc.titleA 8 bits Pipeline Analog to Digital Converter Design for High Speed Camera Application
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