Easily testable logical networks based on a 'widened long flip-flop'

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dc.creatorStukach, Nick
dc.date2008-08-19
dc.date2008-08-20
dc.date.accessioned2026-07-07T09:57:21Z
dc.date.available2026-07-07T09:57:21Z
dc.descriptionThe article describes an attempt to solve at once three basic problems arising at testing a complex digital equipment for defects: 1) the problem of an exponential increasing of the complexity of testing the equipment with the complexity of the equipment; 2) the problem of testing of the tester; 3) the problem of a mutual masking of defects. The proposed solution is nothing more than using certain limitations for connections between usual logical gates. Arbitrary multiple stuck-at-faults are supposed as defects.
dc.description64 pages, including 35 figures and 10 tables
dc.identifierhttps://arxiv.org/abs/0808.2602
dc.identifierhttp://arxiv.org/abs/0808.2602
dc.identifier.urihttp://salesiana.dossiersoluciones.com/handle/123456789/167309
dc.subjectHardware Architecture
dc.subjectB.8; C.4
dc.titleEasily testable logical networks based on a 'widened long flip-flop'
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