Synthesis of Low-Power Digital Circuits Derived from Binary Decision Diagrams

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dc.creatorPopel, Denis V.
dc.date2002-07-04
dc.date.accessioned2026-07-07T03:18:35Z
dc.date.available2026-07-07T03:18:35Z
dc.descriptionThis paper introduces a novel method for synthesizing digital circuits derived from Binary Decision Diagrams (BDDs) that can yield to reduction in power dissipation. The power reduction is achieved by decreasing the switching activity in a circuit while paying close attention to information measures as an optimization criterion. We first present the technique of efficient BDD-based computation of information measures which are used to guide the power optimization procedures. Using this technique, we have developed an algorithm of BDD reordering which leads to reducing the power consumption of the circuits derived from BDDs. Results produced by the synthesis on the ISCAS benchmark circuits are very encouraging.
dc.description4 pages, 3 figures, 1 table, ECCTD'01
dc.identifierhttps://arxiv.org/abs/cs/0207012
dc.identifierhttp://arxiv.org/abs/cs/0207012
dc.identifierECCTD 2001
dc.identifier.urihttp://salesiana.dossiersoluciones.com/handle/123456789/31172
dc.subjectHardware Architecture
dc.subjectB.6.3
dc.titleSynthesis of Low-Power Digital Circuits Derived from Binary Decision Diagrams
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