Performance of a spin-based insulated gate field effect transistor

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dc.creatorHall, Kimberley C.
dc.creatorFlatté, Michael E.
dc.date2006-03-09
dc.date.accessioned2026-07-07T07:02:17Z
dc.date.available2026-07-07T07:02:17Z
dc.descriptionFundamental physical properties limiting the performance of spin field effect transistors are compared to those of ordinary (charge-based) field effect transistors. Instead of raising and lowering a barrier to current flow these spin transistors use static spin-selective barriers and gate control of spin relaxation. The different origins of transistor action lead to distinct size dependences of the power dissipation in these transistors and permit sufficiently small spin-based transistors to surpass the performance of charge-based transistors at room temperature or above. This includes lower threshold voltages, smaller gate capacitances, reduced gate switching energies and smaller source-drain leakage currents.
dc.description4 pages including 3 figures, APL in press
dc.identifierhttps://arxiv.org/abs/cond-mat/0603260
dc.identifierhttp://arxiv.org/abs/cond-mat/0603260
dc.identifierAppl. Phys. Lett. 88, 162503 (2006).
dc.identifierdoi:10.1063/1.2192152
dc.identifier.urihttp://salesiana.dossiersoluciones.com/handle/123456789/108551
dc.subjectMesoscale and Nanoscale Physics
dc.subjectMaterials Science
dc.titlePerformance of a spin-based insulated gate field effect transistor
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