DPA on quasi delay insensitive asynchronous circuits: formalization and improvement

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dc.creatorBouesse, G. F.
dc.creatorRenaudin, M.
dc.creatorDumont, S.
dc.creatorGermain, F.
dc.date2007-10-18
dc.date.accessioned2026-07-07T08:37:01Z
dc.date.available2026-07-07T08:37:01Z
dc.descriptionThe purpose of this paper is to formally specify a flow devoted to the design of Differential Power Analysis (DPA) resistant QDI asynchronous circuits. The paper first proposes a formal modeling of the electrical signature of QDI asynchronous circuits. The DPA is then applied to the formal model in order to identify the source of leakage of this type of circuits. Finally, a complete design flow is specified to minimize the information leakage. The relevancy and efficiency of the approach is demonstrated using the design of an AES crypto-processor.
dc.descriptionSubmitted on behalf of EDAA (http://www.edaa.com/)
dc.identifierhttps://arxiv.org/abs/0710.3443
dc.identifierhttp://arxiv.org/abs/0710.3443
dc.identifierDans Design, Automation and Test in Europe - DATE'05, Munich : Allemagne (2005)
dc.identifierdoi:10.1109/DATE.2005.124
dc.identifier.urihttp://salesiana.dossiersoluciones.com/handle/123456789/140263
dc.subjectHardware Architecture
dc.titleDPA on quasi delay insensitive asynchronous circuits: formalization and improvement
dc.typetext

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