Chip-level CMP Modeling and Smart Dummy for HDP and Conformal CVD Films

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dc.creatorLiu, George Yong
dc.creatorZhang, Ray F.
dc.creatorHsu, Kelvin
dc.creatorCamilletti, Lawrence
dc.date2000-11-09
dc.date.accessioned2026-07-07T03:16:42Z
dc.date.available2026-07-07T03:16:42Z
dc.descriptionChip-level CMP modeling is investigated to obtain the post-CMP film profile thickness across a die from its design layout file and a few film deposition and CMP parameters. The work covers both HDP and conformal CVD film. The experimental CMP results agree well with the modeled results. Different algorithms for filling of dummy structure are compared. A smart algorithm for dummy filling is presented, which achieves maximal pattern-density uniformity and CMP planarity.
dc.description10 pages, 7 figures; for used software, see http://www.cmptechnology.com/
dc.identifierhttps://arxiv.org/abs/cs/0011014
dc.identifierhttp://arxiv.org/abs/cs/0011014
dc.identifierProceedings of CMPMIC 99, pp120-127
dc.identifier.urihttp://salesiana.dossiersoluciones.com/handle/123456789/30453
dc.subjectComputational Engineering, Finance, and Science
dc.subjectB.7.2
dc.titleChip-level CMP Modeling and Smart Dummy for HDP and Conformal CVD Films
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