Running a Quantum Circuit at the Speed of Data
| dc.creator | Isailovic, Nemanja | |
| dc.creator | Whitney, Mark | |
| dc.creator | Patel, Yatish | |
| dc.creator | Kubiatowicz, John | |
| dc.date | 2008-04-30 | |
| dc.date.accessioned | 2026-07-07T09:36:00Z | |
| dc.date.available | 2026-07-07T09:36:00Z | |
| dc.description | We analyze circuits for a number of kernels from popular quantum computing applications, characterizing the hardware resources necessary to take ancilla preparation off the critical path. The result is a chip entirely dominated by ancilla generation circuits. To address this issue, we introduce optimized ancilla factories and analyze their structure and physical layout for ion trap technology. We introduce a new quantum computing architecture with highly concentrated data-only regions surrounded by shared ancilla factories. The results are a reduced dependence on costly teleportation, more efficient distribution of generated ancillae and more than five times speedup over previous proposals. | |
| dc.description | To appear in 35th International Symposium on Computer Architecture (ISCA '08) | |
| dc.identifier | https://arxiv.org/abs/0804.4725 | |
| dc.identifier | http://arxiv.org/abs/0804.4725 | |
| dc.identifier.uri | http://salesiana.dossiersoluciones.com/handle/123456789/160021 | |
| dc.subject | Quantum Physics | |
| dc.title | Running a Quantum Circuit at the Speed of Data | |
| dc.type | text |