Experimental Software Schedulability Estimation For Varied Processor Frequencies

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dc.creatorFabritius, Sampsa
dc.creatorLencevicius, Raimondas
dc.creatorMetz, Edu
dc.creatorRan, Alexander
dc.date2003-02-24
dc.date.accessioned2026-07-07T03:19:29Z
dc.date.available2026-07-07T03:19:29Z
dc.descriptionThis paper describes a new approach to experimentally estimate the application schedulability for various processor frequencies. We use additional workload generated by an artificial high priority routine to simulate the frequency decrease of a processor. Then we estimate the schedulability of applications at different frequencies. The results of such estimation can be used to determine the frequencies and control algorithms of dynamic voltage scaling/dynamic frequency scaling (DVS/DFS) implementations. The paper presents a general problem description, the proposed schedulability estimation method, its analysis and evaluation.
dc.description6 pages, 3 figures, published in the Proceedings of the Symposium on Software Engineering at 21th IASTED International Multi-Conference on Applied Informatics (AI 2003)
dc.identifierhttps://arxiv.org/abs/cs/0302033
dc.identifierhttp://arxiv.org/abs/cs/0302033
dc.identifier.urihttp://salesiana.dossiersoluciones.com/handle/123456789/31478
dc.subjectSoftware Engineering
dc.subjectOperating Systems
dc.subjectD.2.8;D.4.1
dc.titleExperimental Software Schedulability Estimation For Varied Processor Frequencies
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