On the Synthesis of Sequential Reversible Circuit
| dc.creator | Banerjee, Anindita | |
| dc.creator | Pathak, Anirban | |
| dc.date | 2007-07-28 | |
| dc.date.accessioned | 2026-07-07T08:20:54Z | |
| dc.date.available | 2026-07-07T08:20:54Z | |
| dc.description | Reversible circuits for SR flip flop, JK flip flop, D flip flop, T flip flop, Master Slave D flip flop and Master Slave JK flip flop have been provided with three different logical approaches. All the circuits have been optimized with the help of existing local optimization algorithms (e.g. template matching, moving rule and deletion rule) and the optimized sequential circuits have been compared with the earlier proposals for the same. It has been shown that the present proposals have lower gate complexities and lower number of garbage bits compared to the earlier proposals. It has also been shown that the advantage in gate count obtained in some of the earlier proposals by introduction of New gates is an \textcolor{black}{artifact} and if it is allowed then every circuit block (unless there is a measurement) can be reduced to a single gate. Further, it is shown that a reversible flip flop can be constructed even without a feedback. In this context, some important conceptual issues related to the designing and optimization of sequential reversible circuits have also been addressed. | |
| dc.description | 9 pages, 8 Figures, LaTeX 2e, | |
| dc.identifier | https://arxiv.org/abs/0707.4233 | |
| dc.identifier | http://arxiv.org/abs/0707.4233 | |
| dc.identifier.uri | http://salesiana.dossiersoluciones.com/handle/123456789/135205 | |
| dc.subject | Quantum Physics | |
| dc.title | On the Synthesis of Sequential Reversible Circuit | |
| dc.type | text |