Application of a design space exploration tool to enhance interleaver generation

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dc.creatorChavet, Cyrille
dc.creatorCoussy, Philippe
dc.creatorUrard, Pascal
dc.creatorMartin, Eric
dc.date2007-06-20
dc.date.accessioned2026-07-07T08:16:09Z
dc.date.available2026-07-07T08:16:09Z
dc.descriptionThis paper presents a methodology to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall performance of the system is significantly affected by communication architectures, as a consequence the designers need specifically optimized adapters. By explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named Space-Time AdapteR (STAR). Our design flow inputs a C description of Input/Output data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a Resource Constraints Graph (RCG). Design space exploration is then performed through associated tools, to synthesize a STAR component under time-to-market constraints. The proposed approach has been tested to design an industrial data mixing block example: an Ultra-Wideband interleaver.
dc.identifierhttps://arxiv.org/abs/0706.3009
dc.identifierhttp://arxiv.org/abs/0706.3009
dc.identifierProceedings of the European Signal Processing Conference (EUSIPCO-2007) (03/09/2007)
dc.identifier.urihttp://salesiana.dossiersoluciones.com/handle/123456789/133684
dc.subjectHardware Architecture
dc.subjectInformation Theory
dc.titleApplication of a design space exploration tool to enhance interleaver generation
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