Decting Errors in Reversible Circuits With Invariant Relationships

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dc.creatorAlves, Nuno
dc.date2008-12-19
dc.date.accessioned2026-07-07T12:20:55Z
dc.date.available2026-07-07T12:20:55Z
dc.descriptionReversible logic is experience renewed interest as we are approach the limits of CMOS technologies. While physical implementations of reversible gates have yet to materialize, it is safe to assume that they will rely on faulty individual components. In this work we present a present a method to provide fault tolerance to a reversible circuit based on invariant relationships.
dc.identifierhttps://arxiv.org/abs/0812.3871
dc.identifierhttp://arxiv.org/abs/0812.3871
dc.identifier.urihttp://salesiana.dossiersoluciones.com/handle/123456789/213211
dc.subjectHardware Architecture
dc.titleDecting Errors in Reversible Circuits With Invariant Relationships
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