A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks

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dc.creatorHoogvorst, Philippe
dc.creatorGuilley, Sylvain
dc.creatorChaudhuri, Sumanta
dc.creatorDanger, Jean-Luc
dc.creatorBeyrouthy, Taha
dc.creatorFesquet, Laurent
dc.date2008-09-23
dc.date.accessioned2026-07-07T10:04:42Z
dc.date.available2026-07-07T10:04:42Z
dc.descriptionSide-channel attacks are efficient attacks against cryptographic devices. They use only quantities observable from outside, such as the duration and the power consumption. Attacks against synchronous devices using electric observations are facilitated by the fact that all transitions occur simultaneously with some global clock signal. Asynchronous control remove this synchronization and therefore makes it more difficult for the attacker to insulate \emph{interesting intervals}. In addition the coding of data in an asynchronous circuit is inherently more difficult to attack. This article describes the Programmable Logic Block of an asynchronous FPGA resistant against \emph{side-channel attacks}. Additionally it can implement different styles of asynchronous control and of data representation.
dc.description29 pages
dc.identifierhttps://arxiv.org/abs/0809.3942
dc.identifierhttp://arxiv.org/abs/0809.3942
dc.identifier.urihttp://salesiana.dossiersoluciones.com/handle/123456789/169771
dc.subjectCryptography and Security
dc.subjectOther Computer Science
dc.subjectD.4.6; B.2.1
dc.titleA Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks
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