Efficient implementation of GALS systems over commercial synchronous FPGAs: a new approach
| dc.creator | Garcia-Lasheras, Javier D. | |
| dc.date | 2008-02-23 | |
| dc.date.accessioned | 2026-07-07T09:22:55Z | |
| dc.date.available | 2026-07-07T09:22:55Z | |
| dc.description | The new vision presented is aimed to overcome the logic overhead issues that previous works exhibit when applying GALS techniques to programmable logic devices. The proposed new view relies in a 2-phase, bundled data parity based protocol for data transfer and clock generation tasks. The ability of the introduced methodology for smart real-time delay selection allows the implementation of a variety of new methodologies for electromagnetic interference mitigation and device environment changes adaptation. | |
| dc.description | English version of the paper presented in the Spanish Workshop on Reconfigurable Computing and Applications, Zaragoza (2007) | |
| dc.identifier | https://arxiv.org/abs/0802.3441 | |
| dc.identifier | http://arxiv.org/abs/0802.3441 | |
| dc.identifier | "Implementacion eficiente de sistemas GALS sobre FPGAs", Jornadas de Computacion Reconfigurable y Aplicaciones (JCRA'07), Zaragoza (2007) | |
| dc.identifier.uri | http://salesiana.dossiersoluciones.com/handle/123456789/155546 | |
| dc.subject | Hardware Architecture | |
| dc.subject | B.6.1; B.7.1 | |
| dc.title | Efficient implementation of GALS systems over commercial synchronous FPGAs: a new approach | |
| dc.type | text |