Serially Concatenated IRA Codes
| dc.creator | Cheng, Taikun | |
| dc.creator | Sivakumar, Krishnamoorthy | |
| dc.creator | Belzer, Benjamin J. | |
| dc.date | 2007-09-27 | |
| dc.date.accessioned | 2026-07-07T08:32:39Z | |
| dc.date.available | 2026-07-07T08:32:39Z | |
| dc.description | We address the error floor problem of low-density parity check (LDPC) codes on the binary-input additive white Gaussian noise (AWGN) channel, by constructing a serially concatenated code consisting of two systematic irregular repeat accumulate (IRA) component codes connected by an interleaver. The interleaver is designed to prevent stopping-set error events in one of the IRA codes from propagating into stopping set events of the other code. Simulations with two 128-bit rate 0.707 IRA component codes show that the proposed architecture achieves a much lower error floor at higher SNRs, compared to a 16384-bit rate 1/2 IRA code, but incurs an SNR penalty of about 2 dB at low to medium SNRs. Experiments indicate that the SNR penalty can be reduced at larger blocklengths. | |
| dc.description | Forty-Fifth Annual Allerton Conference on Communication, Control, and Computing, 2007, 4 pages, 4 figures | |
| dc.identifier | https://arxiv.org/abs/0709.4466 | |
| dc.identifier | http://arxiv.org/abs/0709.4466 | |
| dc.identifier.uri | http://salesiana.dossiersoluciones.com/handle/123456789/138863 | |
| dc.subject | Information Theory | |
| dc.title | Serially Concatenated IRA Codes | |
| dc.type | text |