Dynamic load-balancing on multi-FPGA systems: a case study

dc.creatorKindratenko, Volodymyr V.
dc.creatorBrunner, Robert J.
dc.creatorMyers, Adam D.
dc.date2007-11-13
dc.date.accessioned2026-07-07T08:42:40Z
dc.date.available2026-07-07T08:42:40Z
dc.descriptionIn this case study, we investigate the impact of workload balance on the performance of multi-FPGA codes. We start with an application in which two distinct kernels run in parallel on two SRC-6 MAP processors. We observe that one of the MAP processors is idle 18% of the time while the other processor is fully utilized. We investigate a task redistribution schema which serializes the execution of the two kernels, yet parallelizes execution of each individual kernel by spreading the workload between two MAP processors. This implementation results in a near 100% utilization of both MAP processors and the overall application performance is improved by 9%.
dc.descriptionOn speeding up 2PCF calculations using field-programmable gate arrays, appeared in Proc. 3rd Annual Reconfigurable Systems Summer Institute - RSSI'07, 2007, 8 pages
dc.identifierhttps://arxiv.org/abs/0711.2034
dc.identifierhttp://arxiv.org/abs/0711.2034
dc.identifier.urihttp://salesiana.dossiersoluciones.com/handle/123456789/142045
dc.subjectAstrophysics
dc.titleDynamic load-balancing on multi-FPGA systems: a case study
dc.typetext

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