Automatic Hardware Synthesis for a Hybrid Reconfigurable CPU Featuring Philips CPLDs

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dc.creatorKastrup, Bernardo
dc.date1998-11-12
dc.date.accessioned2026-07-07T03:23:49Z
dc.date.available2026-07-07T03:23:49Z
dc.descriptionA high-level architecture of a Hybrid Reconfigurable CPU, based on a Philips-supported core processor, is introduced. It features the Philips XPLA2 CPLD as a reconfigurable functional unit. A compilation chain is presented, in which automatic implementation of time-critical program segments in custom hardware is performed. The entire process is transparent from the programmer's point of view. The hardware synthesis module of the chain, which translates segments of assembly code into a hardware netlist, is discussed in details. Application examples are also presented.
dc.description6 pages, 7 figures, PACT '98 Workshop on Reconfigurable Computing
dc.identifierhttps://arxiv.org/abs/cs/9811021
dc.identifierhttp://arxiv.org/abs/cs/9811021
dc.identifier.urihttp://salesiana.dossiersoluciones.com/handle/123456789/33091
dc.subjectProgramming Languages
dc.subjectHardware Architecture
dc.subjectD.3.4; C.1.3
dc.titleAutomatic Hardware Synthesis for a Hybrid Reconfigurable CPU Featuring Philips CPLDs
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