Partial Reversible Gates(PRG) for Reversible BCD Arithmetic
| dc.creator | Thapliyal, Himanshu | |
| dc.creator | Arabnia, Hamid R. | |
| dc.creator | Bajpai, Rajnish | |
| dc.creator | Sharma, Kamal K. | |
| dc.date | 2007-11-16 | |
| dc.date.accessioned | 2026-07-07T08:43:26Z | |
| dc.date.available | 2026-07-07T08:43:26Z | |
| dc.description | IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. Furthermore, in the recent years reversible logic has emerged as a promising computing paradigm having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. The major goal in reversible logic is to minimize the number of reversible gates and garbage outputs. Thus, this paper proposes the novel concept of partial reversible gates that will satisfy the reversibility criteria for specific cases in BCD arithmetic. The partial reversible gate is proposed to minimize the number of reversible gates and garbage outputs, while designing the reversible BCD arithmetic circuits. | |
| dc.description | Published in Proceedings of the 2007 International Conference on Computer Design(CDES'07), Las Vegas, U.S.A, June 2007, pp. 90-91(CSREA Press) | |
| dc.identifier | https://arxiv.org/abs/0711.2674 | |
| dc.identifier | http://arxiv.org/abs/0711.2674 | |
| dc.identifier.uri | http://salesiana.dossiersoluciones.com/handle/123456789/142315 | |
| dc.subject | Hardware Architecture | |
| dc.title | Partial Reversible Gates(PRG) for Reversible BCD Arithmetic | |
| dc.type | text |