Very Fast Chip-level Thermal Analysis

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dc.creatorNakabayashi, K.
dc.creatorNakabayashi, T.
dc.creatorNakajima, K.
dc.date2008-01-07
dc.date.accessioned2026-07-07T08:53:03Z
dc.date.available2026-07-07T08:53:03Z
dc.descriptionWe present a new technique of VLSI chip-level thermal analysis. We extend a newly developed method of solving two dimensional Laplace equations to thermal analysis of four adjacent materials on a mother board. We implement our technique in C and compare its performance to that of a commercial CAD tool. Our experimental results show that our program runs 5.8 and 8.9 times faster while keeping smaller residuals by 5 and 1 order of magnitude, respectively.
dc.descriptionSubmitted on behalf of TIMA Editions (http://irevues.inist.fr/tima-editions)
dc.identifierhttps://arxiv.org/abs/0801.1056
dc.identifierhttp://arxiv.org/abs/0801.1056
dc.identifierDans 13th International Worshop on THERMal INvestigations of ICs and Systems - THERMINIC 2007, Budapest : Hongrie (2007)
dc.identifier.urihttp://salesiana.dossiersoluciones.com/handle/123456789/145486
dc.subjectGeneral Physics
dc.titleVery Fast Chip-level Thermal Analysis
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