Output Width Signal Control In Asynchronous Digital Systems Using Monostable Circuits
Abstract
Description
In present paper, I propose a method for resolving the timing delays for output signals from an asynchronous sequential system. It will be used an example of an asynchronous sequential system that will set up an output signal when an input signal will be set up. The width of the output signal depends on the input signal width, and in this case it is very short. There are many synthesis methods, like using a RC group system, a monostable system in design of the asynchronous digital system or using an external clock signal, CK. In this paper will be used a monostable circuit.
6 pages,exposed on 1st "European Conference on Computer Sciences & Applications" - XA2006, Timisoara, Romania
6 pages,exposed on 1st "European Conference on Computer Sciences & Applications" - XA2006, Timisoara, Romania