Efficient FPGA-based multipliers for F_{3^97} and F_{3^{6*97}}
| dc.creator | Shokrollahi, Jamshid | |
| dc.creator | Gorla, Elisa | |
| dc.creator | Puttmann, Christoph | |
| dc.date | 2007-08-22 | |
| dc.date.accessioned | 2026-07-07T08:24:58Z | |
| dc.date.available | 2026-07-07T08:24:58Z | |
| dc.description | In this work we present a new structure for multiplication in finite fields. This structure is based on a digit-level LFSR (Linear Feedback Shift Register) multiplier in which the area of digit-multipliers are reduced using the Karatsuba method. We compare our results with the other works in the literature for F_{3^97}. We also propose new formulas for multiplication in F_{3^{6*97}}. These new formulas reduce the number of F_{3^97}-multiplications from 18 to 15. The fields F_{3^{97}} and F_{3^{6*97}} are relevant in the context of pairing-based cryptography. | |
| dc.description | 6 pages, 3 figures, to appear in the proceedings of FPL07 | |
| dc.identifier | https://arxiv.org/abs/0708.3022 | |
| dc.identifier | http://arxiv.org/abs/0708.3022 | |
| dc.identifier.uri | http://salesiana.dossiersoluciones.com/handle/123456789/136522 | |
| dc.subject | Cryptography and Security | |
| dc.title | Efficient FPGA-based multipliers for F_{3^97} and F_{3^{6*97}} | |
| dc.type | text |