Introducing a Performance Model for Bandwidth-Limited Loop Kernels

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dc.creatorTreibig, Jan
dc.creatorHager, Georg
dc.date2009-05-06
dc.date.accessioned2026-07-07T13:12:15Z
dc.date.available2026-07-07T13:12:15Z
dc.descriptionWe present a performance model for bandwidth limited loop kernels which is founded on the analysis of modern cache based microarchitectures. This model allows an accurate performance prediction and evaluation for existing instruction codes. It provides an in-depth understanding of how performance for different memory hierarchy levels is made up. The performance of raw memory load, store and copy operations and a stream vector triad are analyzed and benchmarked on three modern x86-type quad-core architectures in order to demonstrate the capabilities of the model.
dc.description8 pages
dc.identifierhttps://arxiv.org/abs/0905.0792
dc.identifierhttp://arxiv.org/abs/0905.0792
dc.identifier.urihttp://salesiana.dossiersoluciones.com/handle/123456789/229524
dc.subjectPerformance
dc.subjectHardware Architecture
dc.titleIntroducing a Performance Model for Bandwidth-Limited Loop Kernels
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