Reducing Average and Peak Temperatures of VLSI CMOS Digital Circuits by Means of Heuristic Scheduling Algorithm

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dc.creatorSzczesniak, Wladyslaw
dc.date2008-01-07
dc.date.accessioned2026-07-07T08:53:00Z
dc.date.available2026-07-07T08:53:00Z
dc.descriptionThis paper presents a BPD (Balanced Power Dissipation) heuristic scheduling algorithm applied to VLSI CMOS digital circuits/systems in order to reduce the global computational demand and provide balanced power dissipation of computational units of the designed digital VLSI CMOS system during the task assignment stage. It results in reduction of the average and peak temperatures of VLSI CMOS digital circuits. The elaborated algorithm is based on balanced power dissipation of local computational (processing) units and does not deteriorate the throughput of the whole VLSI CMOS digital system.
dc.descriptionSubmitted on behalf of TIMA Editions (http://irevues.inist.fr/tima-editions)
dc.identifierhttps://arxiv.org/abs/0801.1029
dc.identifierhttp://arxiv.org/abs/0801.1029
dc.identifierDans 13th International Worshop on THERMal INvestigations of ICs and Systems - THERMINIC 2007, Budapest : Hongrie (2007)
dc.identifier.urihttp://salesiana.dossiersoluciones.com/handle/123456789/145472
dc.subjectGeneral Physics
dc.titleReducing Average and Peak Temperatures of VLSI CMOS Digital Circuits by Means of Heuristic Scheduling Algorithm
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