Performance Evaluation of Packet-to-Cell Segmentation Schemes in Input Buffered Packet Switches

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dc.creatorChristensen, K. J.
dc.creatorYoshigoe, K.
dc.creatorRoginsky, A.
dc.creatorGunther, N. J.
dc.date2004-03-17
dc.date.accessioned2026-07-07T03:21:02Z
dc.date.available2026-07-07T03:21:02Z
dc.descriptionMost input buffered packet switches internally segment variable-length packets into fixed-length cells. The last cell in a segmented packet will contain overhead bytes if the packet length is not evenly divisible by the cell length. Switch speed-up is used to compensate for this overhead. In this paper, we develop an analytical model of a single-server queue where an input stream of packets is segmented into cells for service. Analytical models are developed for M/M/1, M/H2/1, and M/E2/1 queues with a discretized (or quantized) service time. These models and simulation using real packet traces are used to evaluate the effect of speed-up on mean queue length. We propose and evaluate a new method of segmenting a packet trailer and subsequent packet header into a single cell. This cell merging method reduces the required speed-up. No changes to switch-matrix scheduling algorithms are needed. Simulation with a packet trace shows a reduction in the needed speed-up for an iSLIP scheduled input buffered switch.
dc.descriptionTo be presented at the IEEE International Conference on Communications (ICC 2004) Paris, France, June 20-24 2004
dc.identifierhttps://arxiv.org/abs/cs/0403030
dc.identifierhttp://arxiv.org/abs/cs/0403030
dc.identifier.urihttp://salesiana.dossiersoluciones.com/handle/123456789/32046
dc.subjectNetworking and Internet Architecture
dc.subjectPerformance
dc.subjectB.6.3;B.7.1;B.8.2;C.2.1
dc.titlePerformance Evaluation of Packet-to-Cell Segmentation Schemes in Input Buffered Packet Switches
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