Design and Implementation a 8 bits Pipeline Analog to Digital Converter in the Technology 0.6 μm CMOS Process

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dc.creatorPrasetyo, Eri
dc.creatorGinhac, Dominique
dc.creatorPaindavoine, Michel
dc.date2008-08-04
dc.date.accessioned2026-07-07T09:54:32Z
dc.date.available2026-07-07T09:54:32Z
dc.descriptionThis paper describes a 8 bits, 20 Msamples/s pipeline analog-to-digital converter implemented in 0.6 μm CMOS technology with a total power dissipation of 75.47 mW. Circuit techniques used include a precise comparator, operational amplifier and clock management. A switched capacitor is used to sample and multiplying at each stage. Simulation a worst case DNL and INL of 0.75 LSB. The design operate at 5 V dc. The ADC achieves a SNDR of 44.86 dB. keywords : pipeline, switched capacitor, clock management
dc.description5 pages, Conference in Paris
dc.identifierhttps://arxiv.org/abs/0808.0387
dc.identifierhttp://arxiv.org/abs/0808.0387
dc.identifier.urihttp://salesiana.dossiersoluciones.com/handle/123456789/166347
dc.subjectRobotics
dc.subjectComputer Vision and Pattern Recognition
dc.titleDesign and Implementation a 8 bits Pipeline Analog to Digital Converter in the Technology 0.6 μm CMOS Process
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