2026-07-072026-07-07http://salesiana.dossiersoluciones.com/handle/123456789/167340We present a capacitance-voltage study for arrays of vertical InAs nanowires. MOS capacitors are obtained by insulating the nanowires with a conformal 10nm HfO2 layer and using a top Cr/Au metallization as one of the capacitor's electrodes. The described fabrication and characterization technique enables a systematic investigation of the carrier density in the nanowires as well as of the quality of the MOS interface.8 pages, 3 figuresMaterials ScienceOther Condensed Mattertext