InAs Nanowire MOS Capacitors

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dc.creatorRoddaro, Stefano
dc.creatorNilsson, Kristian
dc.creatorAstromskas, Gvidas
dc.creatorSamuelson, Lars
dc.creatorWernersson, Lars-Erik
dc.creatorKarlstrom, Ovol
dc.creatorWacker, Andreas
dc.date2008-06-18
dc.date.accessioned2026-07-07T09:57:26Z
dc.date.available2026-07-07T09:57:26Z
dc.descriptionWe present a capacitance-voltage study for arrays of vertical InAs nanowires. MOS capacitors are obtained by insulating the nanowires with a conformal 10nm HfO2 layer and using a top Cr/Au metallization as one of the capacitor's electrodes. The described fabrication and characterization technique enables a systematic investigation of the carrier density in the nanowires as well as of the quality of the MOS interface.
dc.description8 pages, 3 figures
dc.identifierhttps://arxiv.org/abs/0806.2942
dc.identifierhttp://arxiv.org/abs/0806.2942
dc.identifierAppl. Phys. Lett. 92, 253509 (2008)
dc.identifier.urihttp://salesiana.dossiersoluciones.com/handle/123456789/167340
dc.subjectMaterials Science
dc.subjectOther Condensed Matter
dc.titleInAs Nanowire MOS Capacitors
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