Gate-level simulation of logical state preparation

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dc.creatorStephens, A. M.
dc.creatorDevitt, S. J.
dc.creatorFowler, A. G.
dc.creatorAng, J. C.
dc.creatorHollenberg, L. C. L.
dc.date2006-08-14
dc.date.accessioned2026-07-07T07:26:27Z
dc.date.available2026-07-07T07:26:27Z
dc.descriptionQuantum error correction and fault-tolerant quantum computation are two fundamental concepts which make quantum computing feasible. While providing a theoretical means with which to ensure the arbitrary accuracy of any quantum circuit, fault-tolerant error correction is predicated upon the robust preparation of logical states. An optimal direct circuit and a more complex fault-tolerant circuit for the preparation of the [[7,1,3]] Steane logical-zero are simulated in the presence of discrete quantum errors to quantify the regime within which fault-tolerant preparation of logical states is preferred.
dc.description8 pages, 2 figures
dc.identifierhttps://arxiv.org/abs/quant-ph/0608112
dc.identifierhttp://arxiv.org/abs/quant-ph/0608112
dc.identifier.urihttp://salesiana.dossiersoluciones.com/handle/123456789/117080
dc.subjectQuantum Physics
dc.titleGate-level simulation of logical state preparation
dc.typetext

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