Parasitic Effects Reduction for Wafer-Level Packaging of RF-Mems

Thumbnail Image

Date

Authors

Journal Title

Journal ISSN

Volume Title

Publisher

Abstract

Description

In RF-MEMS packaging, next to the protection of movable structures, optimization of package electrical performance plays a very important role. In this work, a wafer-level packaging process has been investigated and optimized in order to minimize electrical parasitic effects. The RF-MEMS package concept used is based on a wafer-level bonding of a capping silicon substrate to an RF-MEMS wafer. The capping silicon substrate resistivity, substrate thickness and the geometry of through-substrate electrical interconnect vias have been optimized using finite-element electromagnetic simulations (Ansoft HFSS). Test structures for electrical characterization have been designed and after their fabrication, measurement results will be compared with simulations.
Submitted on behalf of TIMA Editions (http://irevues.inist.fr/tima-editions)

Keywords

Other Computer Science

Citation

URI

http://salesiana.dossiersoluciones.com/handle/123456789/143005

Consulte el texto completo en el siguiente enlace:

https://arxiv.org/abs/0711.3275
 http://arxiv.org/abs/0711.3275
 Dans Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS - DTIP 2006, Stresa, Lago Maggiore : Italie (2006)

Collections

arXiv