Parasitic Effects Reduction for Wafer-Level Packaging of RF-Mems

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dc.creatorIannacci, J.
dc.creatorTian, Jason
dc.creatorSinaga, S.
dc.creatorGaddi, R.
dc.creatorGnudi, A.
dc.creatorBartek, M.
dc.date2007-11-21
dc.date.accessioned2026-07-07T08:45:35Z
dc.date.available2026-07-07T08:45:35Z
dc.descriptionIn RF-MEMS packaging, next to the protection of movable structures, optimization of package electrical performance plays a very important role. In this work, a wafer-level packaging process has been investigated and optimized in order to minimize electrical parasitic effects. The RF-MEMS package concept used is based on a wafer-level bonding of a capping silicon substrate to an RF-MEMS wafer. The capping silicon substrate resistivity, substrate thickness and the geometry of through-substrate electrical interconnect vias have been optimized using finite-element electromagnetic simulations (Ansoft HFSS). Test structures for electrical characterization have been designed and after their fabrication, measurement results will be compared with simulations.
dc.descriptionSubmitted on behalf of TIMA Editions (http://irevues.inist.fr/tima-editions)
dc.identifierhttps://arxiv.org/abs/0711.3275
dc.identifierhttp://arxiv.org/abs/0711.3275
dc.identifierDans Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS - DTIP 2006, Stresa, Lago Maggiore : Italie (2006)
dc.identifier.urihttp://salesiana.dossiersoluciones.com/handle/123456789/143005
dc.subjectOther Computer Science
dc.titleParasitic Effects Reduction for Wafer-Level Packaging of RF-Mems
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