Data access optimizations for highly threaded multi-core CPUs with multiple memory controllers

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dc.creatorHager, Georg
dc.creatorZeiser, Thomas
dc.creatorWellein, Gerhard
dc.date2007-12-14
dc.date2008-01-28
dc.date.accessioned2026-07-07T08:56:23Z
dc.date.available2026-07-07T08:56:23Z
dc.descriptionProcessor and system architectures that feature multiple memory controllers are prone to show bottlenecks and erratic performance numbers on codes with regular access patterns. Although such effects are well known in the form of cache thrashing and aliasing conflicts, they become more severe when memory access is involved. Using the new Sun UltraSPARC T2 processor as a prototypical multi-core design, we analyze performance patterns in low-level and application benchmarks and show ways to circumvent bottlenecks by careful data layout and padding.
dc.description12 pages, 7 figures. Accepted for Workshop on Large-Scale Parallel Processing 2008. Revised and extended version
dc.identifierhttps://arxiv.org/abs/0712.2302
dc.identifierhttp://arxiv.org/abs/0712.2302
dc.identifier.urihttp://salesiana.dossiersoluciones.com/handle/123456789/146592
dc.subjectDistributed, Parallel, and Cluster Computing
dc.subjectPerformance
dc.titleData access optimizations for highly threaded multi-core CPUs with multiple memory controllers
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