The BlueGene/L Supercomputer
| dc.creator | Bhanot, Gyan | |
| dc.creator | Chen, Dong | |
| dc.creator | Gara, Alan | |
| dc.creator | Vranas, Pavlos | |
| dc.date | 2002-12-17 | |
| dc.date.accessioned | 2026-07-07T03:38:54Z | |
| dc.date.available | 2026-07-07T03:38:54Z | |
| dc.description | The architecture of the BlueGene/L massively parallel supercomputer is described. Each computing node consists of a single compute ASIC plus 256 MB of external memory. The compute ASIC integrates two 700 MHz PowerPC 440 integer CPU cores, two 2.8 Gflops floating point units, 4 MB of embedded DRAM as cache, a memory controller for external memory, six 1.4 Gbit/s bi-directional ports for a 3-dimensional torus network connection, three 2.8 Gbit/s bi-directional ports for connecting to a global tree network and a Gigabit Ethernet for I/O. 65,536 of such nodes are connected into a 3-d torus with a geometry of 32x32x64. The total peak performance of the system is 360 Teraflops and the total amount of memory is 16 TeraBytes. | |
| dc.description | Lattice2002(Plenary) proceedings, LaTeX, 8 pages 8 figures | |
| dc.identifier | https://arxiv.org/abs/hep-lat/0212030 | |
| dc.identifier | http://arxiv.org/abs/hep-lat/0212030 | |
| dc.identifier.uri | http://salesiana.dossiersoluciones.com/handle/123456789/38725 | |
| dc.subject | High Energy Physics - Lattice | |
| dc.title | The BlueGene/L Supercomputer | |
| dc.type | text |